The present invention relates to the technique for reducing fluctuations in well potential in a semiconductor integrated circuit.
A technique is known, which sets potential in a substrate or a well region (called “well potential”) to power source potential or a different potential in order to control the threshold value of a MOS (Metal Oxide Semiconductor) transistor. Supply of a potential to a well region will be called “well power feed”. The well power feed is performed via a dedicated tap. As examples of documents describing such well power feed, Japanese Unexamined Patent Publication No. 2003-309178 (patent document 1) and Japanese Unexamined Patent Publication No. 2004-319855 (patent document 2) can be mentioned.
Patent document 1 describes a technique for disposing reinforcement power feed cells for performing reinforcement power feed between cells at the time of performing layout by disposing a plurality of cells in series. Each of the cells has an impurity diffusion region for supplying a substrate or well potential different from the power source potential. The reinforcement power feed cell includes an impurity diffusion region to be electrically coupled to an impurity diffusion region in an adjacent cell, and a power feed line provided in a wiring layer formed over the impurity diffusion region and electrically coupled to the impurity diffusion region. A source diffusion region is coupled to a line in a power source wiring layer via a contact.
Patent document 2 describes a layout method realizing high-density integration by reducing the number of taps by determining the proper number of taps for well power feed.